module handshake_pb #(
)(
    input  wire         clk,
    input  wire         rst,
    input  wire         valid_i,
    output wire         ready_o,
    input  wire  [31:0] a,
    input  wire  [31:0] b,
    input  wire  [31:0] c,
    input  wire  [31:0] d,
    input  wire  [31:0] e,
    input  wire  [31:0] f,
    output wire  [31:0] dout,
    input  wire         ready_i,
    output reg          valid_o
    );

    assign ready_o = ~valid_r1 || ready_r1;
    //pre_fetch结构
    //valid_r1为0代表下一级无数据
    //ready_r1代表下一级准备好了读
reg valid_r1;
reg [31:0] r1_ab;
wire valid_r1;
wire valid_r2;
    always_ff @ (posedge clk) begin 
        if(rst)begin
            valid_r1    <= 1'b0;
        end
        else if(ready_o)begin
            valid_r1    <= valid_i;
        end
    end
  
    always_ff @ (posedge clk) begin
        if(ready_o & valid_i)begin
            r1_ab       <= a + b;   //数据信号不复位
        end
    end

    assign ready_r1 = ~valid_r2 || ready_r2;

    reg [31 : 0] r2_abcd;

    always_ff @ (posedge clk) begin 
        if(rst)begin
            valid_r2    <= 1'b0;
        end
        else if(ready_r1)begin
            valid_r2    <= valid_r1;
        end
    end
  
    always_ff @ (posedge clk) begin
        if(ready_r1 & valid_r1)begin
            r2_abcd     <= r1_ab + r1_cd;
        end
    end

    assign ready_r2 = ~valid_r3 || ready_i;
  
    reg [31 : 0] r3;

    always_ff @ (posedge clk) begin 
        if(rst)begin
            valid_r3    <= 1'b0;
        end
        else if(ready_r2)begin
            valid_r3    <= valid_r2;
        end
    end
  
    always_ff @ (posedge clk) begin
        if(ready_r2 & valid_r2)begin
            r3          <= r2_ef + r2_abcd;
        end
    end

    assign dout     = r3;
    assign valid_o  = valid_r3;
endmodule